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Gmane
From: Antti P Miettinen <ananaza <at> iki.fi>
Subject: ARM11MPCore oprofile
Newsgroups: gmane.linux.ports.arm.kernel
Date: Monday 27th October 2008 08:41:25 UTC (over 9 years ago)
Sorry for an obsolete kernel version but the below diff is just for
discussion. With it and a patch to the oprofile user space tools,
I'm seeing somewhat sensible SCU event counts.

How should the oprofile support for ARM11MPCore be fixed properly?
It seems that we want to be able to compile kernels that support
several machines, but different machines can have different IRQ
numbers for the PMU interrupts and the SCU may be at different
address. So should the SCU address and PMU IRQ base be decided at
runtime? The below just assumes that asm/arch/platform.h defines them
statically but that won't work if we want to be able to include
support for several machines into one kernel.

--- linux-2.6.21.6-foo/arch/arm/oprofile/op_model_mpcore.c~	2008-10-20
13:28:47.000000000 +0300
+++ linux-2.6.21.6-foo/arch/arm/oprofile/op_model_mpcore.c	2008-10-26
15:26:55.000000000 +0200
@@ -20,12 +20,12 @@
  *    3: PMN0 on CPU1
  *    4: PMN1 on CPU1
  *    5: CCNT on CPU1
- *    6: PMN0 on CPU1
- *    7: PMN1 on CPU1
- *    8: CCNT on CPU1
- *    9: PMN0 on CPU1
- *   10: PMN1 on CPU1
- *   11: CCNT on CPU1
+ *    6: PMN0 on CPU2
+ *    7: PMN1 on CPU2
+ *    8: CCNT on CPU2
+ *    9: PMN0 on CPU3
+ *   10: PMN1 on CPU3
+ *   11: CCNT on CPU3
  *   12-19: configurable SCU event counters
  */
 
@@ -42,6 +42,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "op_counter.h"
 #include "op_arm_model.h"
@@ -51,7 +52,7 @@
 /*
  * MPCore SCU event monitor support
  */
-#define SCU_EVENTMONITORS_VA_BASE __io_address(REALVIEW_MPCORE_SCU_BASE +
0x10)
+#define SCU_EVENTMONITORS_VA_BASE __io_address(ARM11_MPCORE_SCU_BASE +
0x10)
 
 /*
  * Bitmask of used SCU counters
@@ -78,15 +79,18 @@
 static irqreturn_t scu_em_interrupt(int irq, void *arg)
 {
 	struct eventmonitor __iomem *emc = SCU_EVENTMONITORS_VA_BASE;
-	unsigned int cnt;
+	unsigned int cnt, temp;
 
 	cnt = irq - IRQ_PMU_SCU0;
 	oprofile_add_sample(get_irq_regs(), SCU_COUNTER(cnt));
 	scu_reset_counter(emc, cnt);
 
+	temp = readl(&emc->PMCR);
+	temp &= 0xffff; /* preserve interrupt enable settings */
 	/* Clear overflow flag for this counter */
-	writel(1 << (cnt + 16), &emc->PMCR);
+	temp |= 1 << (cnt + 16);
+	writel(temp, &emc->PMCR);
 
 	return IRQ_HANDLED;
 }
--- linux-2.6.21.6-foo/include/asm-arm/arch-realview/platform.h~	2008-10-20
13:28:47.000000000 +0300
+++ linux-2.6.21.6-foo/include/asm-arm/arch-realview/platform.h	2008-10-25
00:29:43.000000000 +0300
@@ -466,6 +466,8 @@
 #define REALVIEW_CSR_BASE             0x10000000
 #define REALVIEW_CSR_SIZE             0x10000000
 
+#define ARM11_MPCORE_SCU_BASE REALVIEW_MPCORE_SCU_BASE
+
 #endif
 
 /* 	END */


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