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Gmane
From: Alex Shi <alex.shi <at> intel.com>
Subject: [PATCH v10 0/9] X86 TLB flush optimization
Newsgroups: gmane.linux.kernel
Date: Thursday 28th June 2012 01:02:15 UTC (over 4 years ago)
Thank for Fengguang's 0-day build system. It found 2 build errors on 
the first and 7th patch.

So this version fix them, introduce a c_detect_tlb() member into
struct cpu_dev for tlb entries detection of specific CPU vendor.

Thanks all of comments and testing on this patchset!

Alex

[PATCH v10 1/9] x86/tlb_info: get last level TLB entry number of CPU
[PATCH v10 2/9] x86/flush_tlb: try flush_tlb_single one by one in
[PATCH v10 3/9] x86/tlb: fall back to flush all when meet a THP
[PATCH v10 4/9] x86/tlb: add tlb_flushall_shift for specific CPU
[PATCH v10 5/9] x86/tlb: add tlb_flushall_shift knob into debugfs
[PATCH v10 6/9] mm/mmu_gather: enable tlb flush range in generic
[PATCH v10 7/9] x86/tlb: enable tlb flush range support for x86
[PATCH v10 8/9] x86/tlb: replace INVALIDATE_TLB_VECTOR by
[PATCH v10 9/9] x86/tlb: do flush_tlb_kernel_range by 'invlpg'
 
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