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Gmane
From: Jeff Epler <jepler-ixP+gI44yfQ4d9/VWYMlNA <at> public.gmane.org>
Subject: bad news -- rtapi_float_t (volatile double) vs arm architecture
Newsgroups: gmane.linux.distributions.emc.devel
Date: Wednesday 2nd July 2014 14:12:38 UTC (over 2 years ago)
When someone asked today about the bitness of hal_float_t, I was
reminded that as far as I know, nobody ever looked into whether the
ARM-based systems handle atomic stores to volatile doubles.
Unfortunately, the answer seems to be "no".

    LDM, LDC, LDC2, LDRD, STM, STC, STC2, STRD, PUSH, POP, RFE, SRS, VLDM,
    VLDR, VSTM, and VSTR instructions are executed as a sequence of
    word-aligned word accesses. Each 32-bit word access is guaranteed to be
    single-copy atomic. The architecture does not require subsequences of
    two or more word accesses from the sequence to be single-copy atomic.
    http://stackoverflow.com/questions/9857760/can-an-arm-interrupt-occur-in-mid-instruction
    quoting section A3.5.3 of the ARM V7C architecture reference manual.

In fact, 64-bit VLDR and VSTR are the very instructions emitted by gcc for
accesses through a volatile double *vdp in sequences like
    *vdp = *dp * 2; // instruction sequence: vldr / vadd / vstr
or
    *dp = *vdp / 2; // instruction sequence: vldr / vmul / vstr

As a consequence, on ARM architectures where hal_float_t is a typedef
for volatile double, there is a chance that a reader can see a value
which is a word-wise combination of two different values.  

This is unfortunate news for ARM ports.  It looks like a proper ARM port
would have to typedef hal_float_t to float, just like the x86 port did
before 2.5.0, and put up with all the attendant problems, unless there's
another solution I'm not aware of.  This still emits vldr / vstr
instructions, but as they act on 32 bits at a time they are atomic.

Jeff

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